package simple_riscv
import spinal.core._

class plugin1 extends Plugin{
    val setup = create.early{new Area{
        val p2 = getService[plugin2]
        p2.retain()
    }}

    val late = create.late{new Area{
        val io = getService[plugin2].early.io
        io.pc := io.pa + io.pb
        setup.p2.release()
    }}
}

class plugin2 extends Plugin with LockImplt{
    val early = create early new Area{
        val io = new Bundle{
            val pa = in(UInt(2 bits))
            val pb = in(UInt(2 bits))
            val pc = out(UInt(2 bits))
            val pd = out(UInt(2 bits))
        }
    }.setName("def")

    val late = create.late{new Area{
        val io = early.io
        lock.await()
        io.pd := io.pc + 1
    }}
}

object testPlugin extends App{
    val cfg = SpinalConfig(targetDirectory = "hw/gen")
    cfg.generateVerilog(new Framework(Seq(new plugin1, new plugin2)))
}
